1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to an output circuit, a semiconductor memory device having the same and a method of expanding a valid output data window.
2. Description of the Related Art
In order to increase a unit of data bandwidth of a semiconductor memory device, there have been efforts to increase an operating frequency of the semiconductor memory device or to output two units of data in one clock period using a technique commonly referred to as “double data rate.” As the operating frequency of the semiconductor memory device becomes higher, the valid period of output data, i.e., a valid output data window, may decrease. As a result, correctly testing the semiconductor memory device becomes very difficult.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device, and FIG. 2 is a timing diagram illustrating an operation of the semiconductor memory device of FIG. 1 in a normal mode and in a test mode. The semiconductor memory device in FIG. 1 has been disclosed in a Korean Patent Laid-Open Publication No. 10-2004-0105060. In addition, a method of expanding a valid output data window by changing the frequency of the control clock is also disclosed in the Korean Patent Laid-Open Publication No. 10-2004-0105060.
Referring to FIG. 1, the semiconductor memory device includes a memory cell array 11, an output circuit 13 and a mode register set 15. In a normal mode, the output circuit 13 sequentially outputs the data RDIO_0 to RDIO_3 read from the memory cell array 11 through an output pin 17. In a test mode, the output circuit 13 changes data path to continuously output N times (N is a positive integer) the same data read from the memory cell array 11 through the output pin 17. As shown in the timing diagram in FIG. 2 where N is two, two output data DOUT are outputted in one clock cycle in response to the frequency of the clock CLK in a normal mode, and one output data DOUT are outputted in one clock cycle in response to the frequency of the clock CLK in a test mode.
The semiconductor memory device in FIG. 1 may decrease the frequency of the output data, and thus the valid output data window may be increased. The data output path, however, has to be changed in the test mode.